
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

entity master_slave_test is
end master_slave_test;

architecture I2Cwrite of master_slave_test is

  component I2CmasterDemo_mybuf is
    Port ( FPGA_Clk : IN std_logic;
		       I2C_Clk : out std_logic;
    		     I2C_Data : inout std_logic;
    	   	  SW : IN std_logic_vector(3 downto 0);
				  IMG_RST : out std_logic;
				  DataToSend : in std_logic_vector(15 downto 0));
  end component;
  
  component I2Cslave_debug is
    Port ( Clk : in  STD_LOGIC;
           FPGAClk : in std_logic;
           rid_valid : out std_logic;
           register_id : out std_logic_vector(7 downto 0);
           Data_to_send : in std_logic_vector(15 downto 0);
           dout_valid : out std_logic; 
           Data_out : out std_logic_vector(15 downto 0);
           Direction : out std_logic;
           I2C_toBuffer : out std_logic;
           I2C_fromBuffer : in std_logic);
  end component;
  
  signal fpgaclk,i2cclk,i2cdata,rst : std_logic:='0';
  signal sw : std_logic_vector(3 downto 0):="0000";
  
  signal rid : std_logic_vector(7 downto 0);
  signal dts,dout,master_data : std_logic_vector(15 downto 0);
  signal dir,oem_inI2Cdata,oem_outI2Cdata,rid_v,dout_v : std_logic;
begin
  
  fpgaclk<=not fpgaclk after 10 ns;
  
  Master: I2CmasterDemo_mybuf port map(fpgaclk,i2cclk,i2cdata,sw,rst,master_data);
  Slave: I2Cslave_debug port map(i2cclk,fpgaclk,rid_v,rid,dts,dout_v,dout,dir,oem_inI2Cdata,oem_outI2Cdata);
  
  process
  begin
    master_data<="1111000000001111";
    wait for 100 us;
    sw<="1000";
    wait;
  end process;
  
  --------------------------
  --Slave Data signal buffer
  IOBUF_inst : IOBUF 
		generic map (
	  DRIVE => 12, 
			IBUF_DELAY_VALUE => "0", 	-- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
			IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
			IOSTANDARD => "DEFAULT",
			SLEW => "SLOW") 
		port map (
			O => oem_outI2Cdata, 		-- Buffer output
			IO => i2cdata, 	-- Buffer inout port (connect directly to top-level port)
	   	I => oem_inI2Cdata, 		-- Buffer input
			T => dir		-- 3-state enable input
		); 
end I2Cwrite;